sam-falvo’s gists

sam-falvo / tests.lisp

Created July 5, 2020 22:44

My home-brew unit test system for my Equilibrium-cl game, since none of the other CL unit test systems I've tried satisfy my expectations. FiveAM, for example, eats console output (including compiler warnings and errors!) and appears to auto-define (misspelled) special variables without my consent. This is a no-bullshit testing system.

	(defun expand-test (name actual-expr fn expected-expr setup-form teardown-form)
	`(progn
	(defun ,name ()
	(unwind-protect
	(progn
	,setup-form
	(let ((expected ,expected-expr)
	(actual ,actual-expr))
	(unless (,fn actual expected)
	(error "~A: Expected ~A; got ~A" (string ',name) expected actual))))

sam-falvo / gist:5a1626e88ee1481beb9a2026926412f3

Created August 22, 2019 07:17

Using BCPL coroutines to implement object oriented-like functionality. (Performance isn't too bad either)

	GET "libhdr"

	// Define the message selectors for our "object-oriented" interface.

	MANIFEST {
	MSG_INIT = 1; MSG_FREE;
	MSG_TICK;
	MSG_GET_COUNT;
	MSG_GO_DOWN;
	MSG_GO_UP;

sam-falvo / easyAssertFuncs.v

Created February 13, 2017 00:28

Macro templates for creating assert functions in Verilog. (my original work)

	`define NTB(name)\
	`"name``_tb`"

	`define DEFASSERT(name,msb)\
	task assert_``name``;\
	input [``msb``:0] expected;\
	begin\
	if(expected !== ``name``_tb) begin\
	$display("@E %03X %s Expected %X, got %X", story_tb, `NTB(name), expected, ``name``_tb);\
	$stop;\

sam-falvo / mockup.rs

Created January 9, 2017 06:42

Kestrel-3 emulator mockup GUI (output only; no event handling).

	extern crate sdl2;
	extern crate gemini;


	use gemini::{vdi, font};
	use std::string;


	static SDCARD_IOR : [u16; 16] = [
	0b0000000000000000,

sam-falvo / computer.v

Created December 19, 2016 05:17

	`timescale 1ns / 1ps

	// This module implements a subset of the Kestrel-3 computer in a
	// configuration reasonable for use with Verilator simulation.

	module computer(
	output [17:1] ram_adr_i,
	output [15:0] ram_dat_i,
	output [1:0] ram_sel_i,
	output ram_wen_i,

sam-falvo / gist:6d18be9fa564edf7df2fec5d6d1c7da2

Created October 30, 2016 05:34

SIE in software for RISC-V?

	The first thing we need to do when invoking SIE is save the current thread state.
	The invokING thread called us via an ECALL, so some of this state is in mstatus and mepc.
	So, save it.

	_SIE: ; A0 -> SIEBK to invoke.
	csrrw t0, mscratch, x0 ; mscratch = t0, t0 = pointer to current SIEBK.
	sd x1, _X1(t0)
	sd x2, _X2(t0)
	...
	sd x31, _X31(t0)

sam-falvo / prez.txt

Created August 28, 2016 03:13

Presentation material for SVFIG 2016-Aug-27 meeting.


	Intel Decodes CISC to RISC,

	Can We Decode RISC-V to MISC?

	Samuel A. Falvo II
	2016-Aug-27

sam-falvo / sort-benchmarks.fs

Created April 2, 2016 00:56

	500000 constant //dataset

	//dataset value /dataset
	: /dataset-1
	/dataset 1 cells - ;

	create unsorted ( rely on random contents from ASLR )
	16 , 15 , 14 , 13 , 12 , 11 , 10 , 9 , 8 , 7 , 6 , 5 , 4 , 3 , 2 , 1 ,
	//dataset allot

sam-falvo / Generated Assembly Listing.txt

Created September 8, 2015 05:33

RISC-V Output for given subForth source code

	align 8
	dword $0E00000000000000
	emit:
	ld x16 , 0(dsp)
	addi dsp, dsp, 8
	LGP1 :
	auipc gp, 0
	ld x17 , (emit-LGP1 )-8 (gp)
	sb x16 , 0(x17 )
	jalr x0, 0(ra)

sam-falvo / keybase.md

Created May 19, 2015 20:05

Keybase proof

I hereby claim:

I am sam-falvo on github.
I am saf2 (https://keybase.io/saf2) on keybase.
I have a public key whose fingerprint is 07B8 1461 A0DE C658 D4F3 ED4C 62C5 0196 16AF 1914

To claim this, I am signing this object:

Samuel A. Falvo II sam-falvo

Keybase proof