U-Boot phyCORE-i.MX93 v4 test

gistfile1.txt

U-Boot SPL 2025.01-rc2-00132-g50eba6a2f345 (Nov 21 2024 - 08:17:43 +0100)
SoM: PCL-077-23231211I000.1 PCB rev: 1 
M33 prepare ok
WDT:   Started wdog@42490000 with servicing every 1000ms (40s timeout)
Normal Boot
Trying to boot from BOOTROM
Boot Stage: Primary boot
image offset 0x8000, pagesize 0x200, ivt offset 0x0
Load image from 0x49800 by ROM_API
NOTICE:  BL31: v2.8(release):lf-6.1.36-2.1.0-0-g1a3beeab6484
NOTICE:  BL31: Built : 11:39:38, Aug  7 2023


U-Boot 2025.01-rc2-00132-g50eba6a2f345 (Nov 21 2024 - 08:17:43 +0100)

CPU:   i.MX93 rev1.1
Model: PHYTEC phyCORE-i.MX93
DRAM:  2 GiB
Core:  192 devices, 25 uclasses, devicetree: separate
WDT:   Started wdog@42490000 with servicing every 1000ms (40s timeout)
MMC:   FSL_SDHC: 0, FSL_SDHC: 1
Loading Environment from MMC... Reading from redundant MMC(1)... OK
In:    serial@44380000
Out:   serial@44380000
Err:   serial@44380000
Net:   eth0: ethernet@42890000
Hit any key to stop autoboot:  0 
u-boot=> mmc info
Device: FSL_SDHC
Manufacturer ID: 45
OEM: 0
Name: DA6032 
Bus Speed: 100000000
Mode: HS400ES (200MHz)
Rd Block Len: 512
MMC version 5.1
High Capacity: Yes
Capacity: 29.1 GiB
Bus Width: 8-bit DDR
Erase Group Size: 512 KiB
HC WP Group Size: 8 MiB
User Capacity: 29.1 GiB WRREL
Boot Capacity: 4 MiB ENH
RPMB Capacity: 4 MiB ENH
Boot area 0 is not write protected
Boot area 1 is not write protected
u-boot=>