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OpoOpo/cargo_flash_log.txt

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probe-rs server output
Raw
cargo_flash_log.txt
DEBUG cargo_flash > Changed working directory to .
DEBUG probe_rs_cli_util > Running '/home/opoopo/.rustup/toolchains/stable-x86_64-unknown-linux-gnu/bin/cargo' in directory /home/opoopo/Documents/rust/embedded-trainings-2020/advanced/firmware
Flashing /home/opoopo/Documents/rust/embedded-trainings-2020/advanced/firmware/target/thumbv7em-none-eabihf/debug/hello
DEBUG probe_rs::config::registry > Searching registry for chip with name nRF52840_xxAA
INFO probe_rs::flashing::download > Found loadable segment, physical address: 0x00000000, virtual address: 0x00000000, flags: 0x4
INFO probe_rs::flashing::download > Matching section: ".vector_table"
INFO probe_rs::flashing::download > Found loadable segment, physical address: 0x00000100, virtual address: 0x00000100, flags: 0x5
INFO probe_rs::flashing::download > Matching section: ".text"
INFO probe_rs::flashing::download > Found loadable segment, physical address: 0x000024ac, virtual address: 0x000024ac, flags: 0x4
INFO probe_rs::flashing::download > Matching section: ".rodata"
INFO probe_rs::flashing::download > Found loadable segment, physical address: 0x0000353c, virtual address: 0x2003bfa8, flags: 0x6
INFO probe_rs::flashing::download > Matching section: ".data"
INFO probe_rs::flashing::loader > Found 4 loadable sections:
INFO probe_rs::flashing::loader > .vector_table at 00000000 (256 bytes)
INFO probe_rs::flashing::loader > .text at 00000100 (9132 bytes)
INFO probe_rs::flashing::loader > .rodata at 000024AC (4240 bytes)
INFO probe_rs::flashing::loader > .data at 0000353C (8 bytes)
DEBUG probe_rs::probe::cmsisdap::tools > Searching for CMSIS-DAP probes using libusb
DEBUG probe_rs::probe::cmsisdap::tools > Found 0 CMSIS-DAP probes using libusb, searching HID
DEBUG probe_rs::probe::cmsisdap::tools > Found 0 CMSIS-DAP probes total
DEBUG jaylink > libusb 1.0.24.11584
DEBUG jaylink > libusb has capability API: true
DEBUG jaylink > libusb has HID access: true
DEBUG jaylink > libusb has hotplug support: true
DEBUG jaylink > libusb can detach kernel driver: true
DEBUG jaylink > open_usb: device descriptor: DeviceDescriptor {
bLength: 0x12,
bDescriptorType: 0x1,
bcdUSB: 0x200,
bDeviceClass: 0xef,
bDeviceSubClass: 0x2,
bDeviceProtocol: 0x1,
bMaxPacketSize: 0x40,
idVendor: 0x1366,
idProduct: 0x1015,
bcdDevice: 0x100,
iManufacturer: 0x1,
iProduct: 0x2,
iSerialNumber: 0x3,
bNumConfigurations: 0x1,
}
DEBUG jaylink > scanning 4 interfaces
DEBUG jaylink > J-Link interface is #2
DEBUG jaylink > legacy caps: GetHwVersion | ReadConfig | WriteConfig | SpeedInfo | GetMaxBlockSize | GetHwInfo | ResetStopTimed | SelectIf | GetCounters | GetCpuCaps | ExecCpuCmd | Swo | Register | Indicators | TestNetSpeed | GetCapsEx
DEBUG jaylink::capabilities > unknown ext. capability bits: 0xA140817D8DB8EA5A33 truncated to 0x1B8EA5A33 (Reserved0 | GetHwVersion | ReadConfig | WriteConfig | SpeedInfo | GetMaxBlockSize | GetHwInfo | ResetStopTimed | SelectIf | GetCounters | GetCpuCaps | ExecCpuCmd | Swo | Register | Indicators | TestNetSpeed | GetCapsEx | HwJtagWrite)
DEBUG jaylink > extended caps: GetHwVersion | ReadConfig | WriteConfig | SpeedInfo | GetMaxBlockSize | GetHwInfo | ResetStopTimed | SelectIf | GetCounters | GetCpuCaps | ExecCpuCmd | Swo | Register | Indicators | TestNetSpeed | GetCapsEx | HwJtagWrite
DEBUG probe_rs::probe::cmsisdap::tools > Attempting to open 1366:1015 in CMSIS-DAP v1 mode
DEBUG probe_rs::probe::stlink::usb_interface > Acquired libusb context.
DEBUG jaylink > open_usb: device descriptor: DeviceDescriptor {
bLength: 0x12,
bDescriptorType: 0x1,
bcdUSB: 0x200,
bDeviceClass: 0xef,
bDeviceSubClass: 0x2,
bDeviceProtocol: 0x1,
bMaxPacketSize: 0x40,
idVendor: 0x1366,
idProduct: 0x1015,
bcdDevice: 0x100,
iManufacturer: 0x1,
iProduct: 0x2,
iSerialNumber: 0x3,
bNumConfigurations: 0x1,
}
DEBUG jaylink > scanning 4 interfaces
DEBUG jaylink > J-Link interface is #2
DEBUG jaylink > legacy caps: GetHwVersion | ReadConfig | WriteConfig | SpeedInfo | GetMaxBlockSize | GetHwInfo | ResetStopTimed | SelectIf | GetCounters | GetCpuCaps | ExecCpuCmd | Swo | Register | Indicators | TestNetSpeed | GetCapsEx
DEBUG jaylink::capabilities > unknown ext. capability bits: 0xA140817D8DB8EA5A33 truncated to 0x1B8EA5A33 (Reserved0 | GetHwVersion | ReadConfig | WriteConfig | SpeedInfo | GetMaxBlockSize | GetHwInfo | ResetStopTimed | SelectIf | GetCounters | GetCpuCaps | ExecCpuCmd | Swo | Register | Indicators | TestNetSpeed | GetCapsEx | HwJtagWrite)
DEBUG jaylink > extended caps: GetHwVersion | ReadConfig | WriteConfig | SpeedInfo | GetMaxBlockSize | GetHwInfo | ResetStopTimed | SelectIf | GetCounters | GetCpuCaps | ExecCpuCmd | Swo | Register | Indicators | TestNetSpeed | GetCapsEx | HwJtagWrite
INFO cargo_flash > Protocol speed 0 kHz
DEBUG probe_rs::probe::jlink > Attaching to J-Link
DEBUG probe_rs::probe::jlink > Attaching with protocol 'SWD'
INFO probe_rs::probe::jlink > J-Link: S/N: 683287186
DEBUG probe_rs::probe::jlink > J-Link: Capabilities: GetHwVersion | ReadConfig | WriteConfig | SpeedInfo | GetMaxBlockSize | GetHwInfo | ResetStopTimed | SelectIf | GetCounters | GetCpuCaps | ExecCpuCmd | Swo | Register | Indicators | TestNetSpeed | GetCapsEx | HwJtagWrite
INFO probe_rs::probe::jlink > J-Link: Firmware version: J-Link OB-SAM3U128-V2-NordicSemi compiled Mar 17 2020 14:43:00
INFO probe_rs::probe::jlink > J-Link: Hardware version: J-Link 1.0.0
INFO probe_rs::probe::jlink > J-Link: Target voltage: 3.30 V
DEBUG probe_rs::probe::jlink::swd > Performing line reset!
DEBUG probe_rs::probe::jlink > Sucessfully switched to SWD
DEBUG probe_rs::probe::jlink > Attached succesfully
DEBUG probe_rs::probe::jlink::swd > Performing 1 transfers (0 additional transfers)
DEBUG probe_rs::probe::jlink::swd > Transfer result 0: Ok(2ba01477)
DEBUG probe_rs::architecture::arm::communication_interface > Debug Port version: DPv1
DEBUG probe_rs::architecture::arm::dp > Reading DP register DPIDR
DEBUG probe_rs::probe::jlink::swd > Performing 1 transfers (0 additional transfers)
DEBUG probe_rs::probe::jlink::swd > Transfer result 0: Ok(2ba01477)
DEBUG probe_rs::architecture::arm::dp > Read DP register DPIDR, value=0x2ba01477
DEBUG probe_rs::architecture::arm::communication_interface > DebugPort ID: DebugPortId {
revision: 0x2,
part_no: 0xba,
version: DPv1,
min_dp_support: NotImplemented,
designer: JEP106Code({ cc: 0x04, id: 0x3b } => Some("ARM Ltd")),
}
DEBUG probe_rs::architecture::arm::dp > Writing DP register ABORT, value=0x0000001e
DEBUG probe_rs::probe::jlink::swd > Performing 1 transfers (0 additional transfers)
DEBUG probe_rs::probe::jlink::swd > Transfer result 0: Ok(0)
DEBUG probe_rs::architecture::arm::dp > Writing DP register SELECT, value=0x00000000
DEBUG probe_rs::probe::jlink::swd > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::swd > Transfer result 0: Ok(0)
DEBUG probe_rs::probe::jlink::swd > Transfer result 1: Ok(0)
DEBUG probe_rs::architecture::arm::communication_interface > Requesting debug power
DEBUG probe_rs::architecture::arm::dp > Writing DP register CTRL/STAT, value=0x50000001
DEBUG probe_rs::probe::jlink::swd > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::swd > Transfer result 0: Ok(0)
DEBUG probe_rs::probe::jlink::swd > Transfer result 1: Ok(0)
DEBUG probe_rs::architecture::arm::dp > Reading DP register CTRL/STAT
DEBUG probe_rs::probe::jlink::swd > Performing 1 transfers (0 additional transfers)
DEBUG probe_rs::probe::jlink::swd > Transfer result 0: Ok(f0000041)
DEBUG probe_rs::architecture::arm::dp > Read DP register CTRL/STAT, value=0xf0000041
DEBUG probe_rs::architecture::arm::communication_interface > Reading register IDR
DEBUG probe_rs::architecture::arm::communication_interface > Changing AP to 0, AP_BANK_SEL to 15
DEBUG probe_rs::architecture::arm::dp > Writing DP register SELECT, value=0x000000f0
DEBUG probe_rs::probe::jlink::swd > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::swd > Transfer result 0: Ok(0)
DEBUG probe_rs::probe::jlink::swd > Transfer result 1: Ok(0)
DEBUG probe_rs::probe::jlink::swd > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::swd > Transfer result 0: Ok(0)
DEBUG probe_rs::probe::jlink::swd > Transfer result 1: Ok(24770011)
DEBUG probe_rs::architecture::arm::communication_interface > Read register IDR, value=0x24770011
DEBUG probe_rs::architecture::arm::communication_interface > Reading register IDR
DEBUG probe_rs::architecture::arm::communication_interface > Changing AP to 1, AP_BANK_SEL to 15
DEBUG probe_rs::architecture::arm::dp > Writing DP register SELECT, value=0x010000f0
DEBUG probe_rs::probe::jlink::swd > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::swd > Transfer result 0: Ok(0)
DEBUG probe_rs::probe::jlink::swd > Transfer result 1: Ok(24770011)
DEBUG probe_rs::probe::jlink::swd > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::swd > Transfer result 0: Ok(24770011)
DEBUG probe_rs::probe::jlink::swd > Transfer result 1: Ok(2880000)
DEBUG probe_rs::architecture::arm::communication_interface > Read register IDR, value=0x2880000
DEBUG probe_rs::architecture::arm::communication_interface > Reading register IDR
DEBUG probe_rs::architecture::arm::communication_interface > Changing AP to 2, AP_BANK_SEL to 15
DEBUG probe_rs::architecture::arm::dp > Writing DP register SELECT, value=0x020000f0
DEBUG probe_rs::probe::jlink::swd > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::swd > Transfer result 0: Ok(0)
DEBUG probe_rs::probe::jlink::swd > Transfer result 1: Ok(2880000)
DEBUG probe_rs::probe::jlink::swd > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::swd > Transfer result 0: Ok(2880000)
DEBUG probe_rs::probe::jlink::swd > Transfer result 1: Ok(0)
DEBUG probe_rs::architecture::arm::communication_interface > Read register IDR, value=0x0
DEBUG probe_rs::architecture::arm::communication_interface > Reading register IDR
DEBUG probe_rs::architecture::arm::communication_interface > Changing AP to 0, AP_BANK_SEL to 15
DEBUG probe_rs::architecture::arm::dp > Writing DP register SELECT, value=0x000000f0
DEBUG probe_rs::probe::jlink::swd > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::swd > Transfer result 0: Ok(0)
DEBUG probe_rs::probe::jlink::swd > Transfer result 1: Ok(0)
DEBUG probe_rs::probe::jlink::swd > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::swd > Transfer result 0: Ok(0)
DEBUG probe_rs::probe::jlink::swd > Transfer result 1: Ok(24770011)
DEBUG probe_rs::architecture::arm::communication_interface > Read register IDR, value=0x24770011
DEBUG probe_rs::architecture::arm::communication_interface > Reading register BASE
DEBUG probe_rs::probe::jlink::swd > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::swd > Transfer result 0: Ok(24770011)
DEBUG probe_rs::probe::jlink::swd > Transfer result 1: Ok(e00ff003)
DEBUG probe_rs::architecture::arm::communication_interface > Read register BASE, value=0xe00ff003
DEBUG probe_rs::architecture::arm::communication_interface > Reading register BASE2
DEBUG probe_rs::probe::jlink::swd > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::swd > Transfer result 0: Ok(e00ff003)
DEBUG probe_rs::probe::jlink::swd > Transfer result 1: Ok(0)
DEBUG probe_rs::architecture::arm::communication_interface > Read register BASE2, value=0x0
DEBUG probe_rs::architecture::arm::communication_interface > Reading register CSW
DEBUG probe_rs::architecture::arm::communication_interface > Changing AP to 0, AP_BANK_SEL to 0
DEBUG probe_rs::architecture::arm::dp > Writing DP register SELECT, value=0x00000000
DEBUG probe_rs::probe::jlink::swd > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::swd > Transfer result 0: Ok(0)
DEBUG probe_rs::probe::jlink::swd > Transfer result 1: Ok(0)
DEBUG probe_rs::probe::jlink::swd > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::swd > Transfer result 0: Ok(0)
DEBUG probe_rs::probe::jlink::swd > Transfer result 1: Ok(23000052)
DEBUG probe_rs::architecture::arm::communication_interface > Read register CSW, value=0x23000052
DEBUG probe_rs::architecture::arm::communication_interface > Writing register CSW, value=CSW { DbgSwEnable: 1, HNONSEC: 1, PROT: 6, CACHE: 3, SPIDEN: 0, _RES0: 0, MTE: 0, Type: 0, Mode: 0, TrinProg: 0, DeviceEn: 0, AddrInc: Single, _RES1: 0, SIZE: U8 }
DEBUG probe_rs::probe::jlink::swd > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::swd > Transfer result 0: Ok(0)
DEBUG probe_rs::probe::jlink::swd > Transfer result 1: Ok(23000052)
DEBUG probe_rs::architecture::arm::communication_interface > Reading register CSW
DEBUG probe_rs::probe::jlink::swd > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::swd > Transfer result 0: Ok(23000052)
DEBUG probe_rs::probe::jlink::swd > Transfer result 1: Ok(23000050)
DEBUG probe_rs::architecture::arm::communication_interface > Read register CSW, value=0x23000050
DEBUG probe_rs::architecture::arm::communication_interface > Writing register CSW, value=CSW { DbgSwEnable: 0, HNONSEC: 0, PROT: 2, CACHE: 3, SPIDEN: 0, _RES0: 0, MTE: 0, Type: 0, Mode: 0, TrinProg: 0, DeviceEn: 1, AddrInc: Single, _RES1: 0, SIZE: U32 }
DEBUG probe_rs::probe::jlink::swd > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::swd > Transfer result 0: Ok(0)
DEBUG probe_rs::probe::jlink::swd > Transfer result 1: Ok(23000050)
DEBUG probe_rs::architecture::arm::communication_interface > HNONSEC supported: false
DEBUG probe_rs::architecture::arm::communication_interface > AP 0: MemoryAp(MemoryApInformation { port_number: 0, only_32bit_data_size: false, debug_base_address: 3759140864, supports_hnonsec: false })
DEBUG probe_rs::architecture::arm::communication_interface > Reading register IDR
DEBUG probe_rs::architecture::arm::communication_interface > Changing AP to 1, AP_BANK_SEL to 15
DEBUG probe_rs::architecture::arm::dp > Writing DP register SELECT, value=0x010000f0
DEBUG probe_rs::probe::jlink::swd > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::swd > Transfer result 0: Ok(0)
DEBUG probe_rs::probe::jlink::swd > Transfer result 1: Ok(23000050)
DEBUG probe_rs::probe::jlink::swd > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::swd > Transfer result 0: Ok(23000050)
DEBUG probe_rs::probe::jlink::swd > Transfer result 1: Ok(2880000)
DEBUG probe_rs::architecture::arm::communication_interface > Read register IDR, value=0x2880000
DEBUG probe_rs::architecture::arm::communication_interface > AP 1: Other { port_number: 1 }
DEBUG probe_rs::architecture::arm::communication_interface > Writing register CSW, value=CSW { DbgSwEnable: 0, HNONSEC: 1, PROT: 2, CACHE: 3, SPIDEN: 0, _RES0: 0, MTE: 0, Type: 0, Mode: 0, TrinProg: 0, DeviceEn: 0, AddrInc: Single, _RES1: 0, SIZE: U32 }
DEBUG probe_rs::architecture::arm::communication_interface > Changing AP to 0, AP_BANK_SEL to 0
DEBUG probe_rs::architecture::arm::dp > Writing DP register SELECT, value=0x00000000
DEBUG probe_rs::probe::jlink::swd > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::swd > Transfer result 0: Ok(0)
DEBUG probe_rs::probe::jlink::swd > Transfer result 1: Ok(2880000)
DEBUG probe_rs::probe::jlink::swd > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::swd > Transfer result 0: Ok(0)
DEBUG probe_rs::probe::jlink::swd > Transfer result 1: Ok(2880000)
DEBUG probe_rs::architecture::arm::communication_interface > Writing register TAR, value=TAR { address: e000edf0 }
DEBUG probe_rs::probe::jlink::swd > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::swd > Transfer result 0: Ok(0)
DEBUG probe_rs::probe::jlink::swd > Transfer result 1: Ok(2880000)
DEBUG probe_rs::architecture::arm::communication_interface > Reading register DRW
DEBUG probe_rs::probe::jlink::swd > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::swd > Transfer result 0: Ok(2880000)
DEBUG probe_rs::probe::jlink::swd > Transfer result 1: Ok(3030003)
DEBUG probe_rs::architecture::arm::communication_interface > Read register DRW, value=0x3030003
DEBUG probe_rs::architecture::arm::communication_interface > Writing register TAR, value=TAR { address: e000ed30 }
DEBUG probe_rs::probe::jlink::swd > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::swd > Transfer result 0: Ok(0)
DEBUG probe_rs::probe::jlink::swd > Transfer result 1: Ok(3030003)
DEBUG probe_rs::architecture::arm::communication_interface > Reading register DRW
DEBUG probe_rs::probe::jlink::swd > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::swd > Transfer result 0: Ok(3030003)
DEBUG probe_rs::probe::jlink::swd > Transfer result 1: Ok(2)
DEBUG probe_rs::architecture::arm::communication_interface > Read register DRW, value=0x2
DEBUG probe_rs::architecture::arm::core::m4 > Core was halted when connecting, reason: Breakpoint
DEBUG probe_rs::architecture::arm::communication_interface > Writing register TAR, value=TAR { address: e000ed30 }
DEBUG probe_rs::probe::jlink::swd > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::swd > Transfer result 0: Ok(0)
DEBUG probe_rs::probe::jlink::swd > Transfer result 1: Ok(2)
DEBUG probe_rs::architecture::arm::communication_interface > Writing register DRW, value=DRW { data: 1f }
DEBUG probe_rs::probe::jlink::swd > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::swd > Transfer result 0: Ok(0)
DEBUG probe_rs::probe::jlink::swd > Transfer result 1: Ok(2)
DEBUG probe_rs::architecture::arm::communication_interface > Writing register TAR, value=TAR { address: e000edf0 }
DEBUG probe_rs::probe::jlink::swd > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::swd > Transfer result 0: Ok(0)
DEBUG probe_rs::probe::jlink::swd > Transfer result 1: Ok(2)
DEBUG probe_rs::architecture::arm::communication_interface > Writing register DRW, value=DRW { data: a05f0001 }
DEBUG probe_rs::probe::jlink::swd > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::swd > Transfer result 0: Ok(0)
DEBUG probe_rs::probe::jlink::swd > Transfer result 1: Ok(2)
DEBUG probe_rs::architecture::arm::communication_interface > Writing register CSW, value=CSW { DbgSwEnable: 0, HNONSEC: 1, PROT: 2, CACHE: 3, SPIDEN: 0, _RES0: 0, MTE: 0, Type: 0, Mode: 0, TrinProg: 0, DeviceEn: 0, AddrInc: Single, _RES1: 0, SIZE: U32 }
DEBUG probe_rs::probe::jlink::swd > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::swd > Transfer result 0: Ok(0)
DEBUG probe_rs::probe::jlink::swd > Transfer result 1: Ok(2)
DEBUG probe_rs::architecture::arm::communication_interface > Writing register TAR, value=TAR { address: e0002000 }
DEBUG probe_rs::probe::jlink::swd > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::swd > Transfer result 0: Ok(0)
DEBUG probe_rs::probe::jlink::swd > Transfer result 1: Ok(2)
DEBUG probe_rs::architecture::arm::communication_interface > Reading register DRW
DEBUG probe_rs::probe::jlink::swd > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::swd > Transfer result 0: Ok(2)
DEBUG probe_rs::probe::jlink::swd > Transfer result 1: Ok(261)
DEBUG probe_rs::architecture::arm::communication_interface > Read register DRW, value=0x261
DEBUG probe_rs::architecture::arm::communication_interface > Writing register TAR, value=TAR { address: e0002000 }
DEBUG probe_rs::probe::jlink::swd > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::swd > Transfer result 0: Ok(0)
DEBUG probe_rs::probe::jlink::swd > Transfer result 1: Ok(261)
DEBUG probe_rs::architecture::arm::communication_interface > Reading register DRW
DEBUG probe_rs::probe::jlink::swd > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::swd > Transfer result 0: Ok(261)
DEBUG probe_rs::probe::jlink::swd > Transfer result 1: Ok(261)
DEBUG probe_rs::architecture::arm::communication_interface > Read register DRW, value=0x261
DEBUG probe_rs::architecture::arm::communication_interface > Writing register TAR, value=TAR { address: e0002008 }
DEBUG probe_rs::probe::jlink::swd > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::swd > Transfer result 0: Ok(0)
DEBUG probe_rs::probe::jlink::swd > Transfer result 1: Ok(261)
DEBUG probe_rs::architecture::arm::communication_interface > Reading register DRW
DEBUG probe_rs::probe::jlink::swd > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::swd > Transfer result 0: Ok(261)
DEBUG probe_rs::probe::jlink::swd > Transfer result 1: Ok(0)
DEBUG probe_rs::architecture::arm::communication_interface > Read register DRW, value=0x0
DEBUG probe_rs::architecture::arm::communication_interface > Writing register TAR, value=TAR { address: e0002000 }
DEBUG probe_rs::probe::jlink::swd > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::swd > Transfer result 0: Ok(0)
DEBUG probe_rs::probe::jlink::swd > Transfer result 1: Ok(0)
DEBUG probe_rs::architecture::arm::communication_interface > Reading register DRW
DEBUG probe_rs::probe::jlink::swd > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::swd > Transfer result 0: Ok(0)
DEBUG probe_rs::probe::jlink::swd > Transfer result 1: Ok(261)
DEBUG probe_rs::architecture::arm::communication_interface > Read register DRW, value=0x261
DEBUG probe_rs::architecture::arm::communication_interface > Writing register TAR, value=TAR { address: e000200c }
DEBUG probe_rs::probe::jlink::swd > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::swd > Transfer result 0: Ok(0)
DEBUG probe_rs::probe::jlink::swd > Transfer result 1: Ok(261)
DEBUG probe_rs::architecture::arm::communication_interface > Reading register DRW
DEBUG probe_rs::probe::jlink::swd > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::swd > Transfer result 0: Ok(261)
DEBUG probe_rs::probe::jlink::swd > Transfer result 1: Ok(0)
DEBUG probe_rs::architecture::arm::communication_interface > Read register DRW, value=0x0
DEBUG probe_rs::architecture::arm::communication_interface > Writing register TAR, value=TAR { address: e0002000 }
DEBUG probe_rs::probe::jlink::swd > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::swd > Transfer result 0: Ok(0)
DEBUG probe_rs::probe::jlink::swd > Transfer result 1: Ok(0)
DEBUG probe_rs::architecture::arm::communication_interface > Reading register DRW
DEBUG probe_rs::probe::jlink::swd > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::swd > Transfer result 0: Ok(0)
DEBUG probe_rs::probe::jlink::swd > Transfer result 1: Ok(261)
DEBUG probe_rs::architecture::arm::communication_interface > Read register DRW, value=0x261
DEBUG probe_rs::architecture::arm::communication_interface > Writing register TAR, value=TAR { address: e0002010 }
DEBUG probe_rs::probe::jlink::swd > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::swd > Transfer result 0: Ok(0)
DEBUG probe_rs::probe::jlink::swd > Transfer result 1: Ok(261)
DEBUG probe_rs::architecture::arm::communication_interface > Reading register DRW
DEBUG probe_rs::probe::jlink::swd > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::swd > Transfer result 0: Ok(261)
DEBUG probe_rs::probe::jlink::swd > Transfer result 1: Ok(0)
DEBUG probe_rs::architecture::arm::communication_interface > Read register DRW, value=0x0
DEBUG probe_rs::architecture::arm::communication_interface > Writing register TAR, value=TAR { address: e0002000 }
DEBUG probe_rs::probe::jlink::swd > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::swd > Transfer result 0: Ok(0)
DEBUG probe_rs::probe::jlink::swd > Transfer result 1: Ok(0)
DEBUG probe_rs::architecture::arm::communication_interface > Reading register DRW
DEBUG probe_rs::probe::jlink::swd > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::swd > Transfer result 0: Ok(0)
DEBUG probe_rs::probe::jlink::swd > Transfer result 1: Ok(261)
DEBUG probe_rs::architecture::arm::communication_interface > Read register DRW, value=0x261
DEBUG probe_rs::architecture::arm::communication_interface > Writing register TAR, value=TAR { address: e0002014 }
DEBUG probe_rs::probe::jlink::swd > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::swd > Transfer result 0: Ok(0)
DEBUG probe_rs::probe::jlink::swd > Transfer result 1: Ok(261)
DEBUG probe_rs::architecture::arm::communication_interface > Reading register DRW
DEBUG probe_rs::probe::jlink::swd > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::swd > Transfer result 0: Ok(261)
DEBUG probe_rs::probe::jlink::swd > Transfer result 1: Ok(0)
DEBUG probe_rs::architecture::arm::communication_interface > Read register DRW, value=0x0
DEBUG probe_rs::architecture::arm::communication_interface > Writing register TAR, value=TAR { address: e0002000 }
DEBUG probe_rs::probe::jlink::swd > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::swd > Transfer result 0: Ok(0)
DEBUG probe_rs::probe::jlink::swd > Transfer result 1: Ok(0)
DEBUG probe_rs::architecture::arm::communication_interface > Reading register DRW
DEBUG probe_rs::probe::jlink::swd > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::swd > Transfer result 0: Ok(0)
DEBUG probe_rs::probe::jlink::swd > Transfer result 1: Ok(261)
DEBUG probe_rs::architecture::arm::communication_interface > Read register DRW, value=0x261
DEBUG probe_rs::architecture::arm::communication_interface > Writing register TAR, value=TAR { address: e0002018 }
DEBUG probe_rs::probe::jlink::swd > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::swd > Transfer result 0: Ok(0)
DEBUG probe_rs::probe::jlink::swd > Transfer result 1: Ok(261)
DEBUG probe_rs::architecture::arm::communication_interface > Reading register DRW
DEBUG probe_rs::probe::jlink::swd > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::swd > Transfer result 0: Ok(261)
DEBUG probe_rs::probe::jlink::swd > Transfer result 1: Ok(0)
DEBUG probe_rs::architecture::arm::communication_interface > Read register DRW, value=0x0
DEBUG probe_rs::architecture::arm::communication_interface > Writing register TAR, value=TAR { address: e0002000 }
DEBUG probe_rs::probe::jlink::swd > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::swd > Transfer result 0: Ok(0)
DEBUG probe_rs::probe::jlink::swd > Transfer result 1: Ok(0)
DEBUG probe_rs::architecture::arm::communication_interface > Reading register DRW
DEBUG probe_rs::probe::jlink::swd > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::swd > Transfer result 0: Ok(0)
DEBUG probe_rs::probe::jlink::swd > Transfer result 1: Ok(261)
DEBUG probe_rs::architecture::arm::communication_interface > Read register DRW, value=0x261
DEBUG probe_rs::architecture::arm::communication_interface > Writing register TAR, value=TAR { address: e000201c }
DEBUG probe_rs::probe::jlink::swd > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::swd > Transfer result 0: Ok(0)
DEBUG probe_rs::probe::jlink::swd > Transfer result 1: Ok(261)
DEBUG probe_rs::architecture::arm::communication_interface > Reading register DRW
DEBUG probe_rs::probe::jlink::swd > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::swd > Transfer result 0: Ok(261)
DEBUG probe_rs::probe::jlink::swd > Transfer result 1: Ok(0)
DEBUG probe_rs::architecture::arm::communication_interface > Read register DRW, value=0x0
Finished in 8.354s
Raw
probe-rs_log.txt
Starting "probe-rs-debugger" as a DAP Protocol server
Listening for requests on :127.0.0.1:50001
..Starting session from :127.0.0.1:45102
[2021-07-05T12:06:30Z DEBUG probe_rs::probe::cmsisdap::tools] Searching for CMSIS-DAP probes using libusb
[2021-07-05T12:06:30Z DEBUG probe_rs::probe::cmsisdap::tools] Found 0 CMSIS-DAP probes using libusb, searching HID
[2021-07-05T12:06:30Z DEBUG probe_rs::probe::cmsisdap::tools] Found 0 CMSIS-DAP probes total
[2021-07-05T12:06:30Z DEBUG jaylink] libusb 1.0.24.11584
[2021-07-05T12:06:30Z DEBUG jaylink] libusb has capability API: true
[2021-07-05T12:06:30Z DEBUG jaylink] libusb has HID access: true
[2021-07-05T12:06:30Z DEBUG jaylink] libusb has hotplug support: true
[2021-07-05T12:06:30Z DEBUG jaylink] libusb can detach kernel driver: true
[2021-07-05T12:06:30Z DEBUG jaylink] open_usb: device descriptor: DeviceDescriptor {
bLength: 0x12,
bDescriptorType: 0x1,
bcdUSB: 0x200,
bDeviceClass: 0xef,
bDeviceSubClass: 0x2,
bDeviceProtocol: 0x1,
bMaxPacketSize: 0x40,
idVendor: 0x1366,
idProduct: 0x1015,
bcdDevice: 0x100,
iManufacturer: 0x1,
iProduct: 0x2,
iSerialNumber: 0x3,
bNumConfigurations: 0x1,
}
[2021-07-05T12:06:30Z DEBUG jaylink] scanning 4 interfaces
[2021-07-05T12:06:30Z DEBUG jaylink] J-Link interface is #2
[2021-07-05T12:06:30Z DEBUG jaylink] legacy caps: GetHwVersion | ReadConfig | WriteConfig | SpeedInfo | GetMaxBlockSize | GetHwInfo | ResetStopTimed | SelectIf | GetCounters | GetCpuCaps | ExecCpuCmd | Swo | Register | Indicators | TestNetSpeed | GetCapsEx
[2021-07-05T12:06:30Z DEBUG jaylink::capabilities] unknown ext. capability bits: 0xA140817D8DB8EA5A33 truncated to 0x1B8EA5A33 (Reserved0 | GetHwVersion | ReadConfig | WriteConfig | SpeedInfo | GetMaxBlockSize | GetHwInfo | ResetStopTimed | SelectIf | GetCounters | GetCpuCaps | ExecCpuCmd | Swo | Register | Indicators | TestNetSpeed | GetCapsEx | HwJtagWrite)
[2021-07-05T12:06:30Z DEBUG jaylink] extended caps: GetHwVersion | ReadConfig | WriteConfig | SpeedInfo | GetMaxBlockSize | GetHwInfo | ResetStopTimed | SelectIf | GetCounters | GetCpuCaps | ExecCpuCmd | Swo | Register | Indicators | TestNetSpeed | GetCapsEx | HwJtagWrite
[2021-07-05T12:06:30Z DEBUG probe_rs::probe::cmsisdap::tools] Attempting to open 1366:1015 in CMSIS-DAP v1 mode
[2021-07-05T12:06:30Z DEBUG probe_rs::probe::stlink::usb_interface] Acquired libusb context.
[2021-07-05T12:06:30Z DEBUG jaylink] open_usb: device descriptor: DeviceDescriptor {
bLength: 0x12,
bDescriptorType: 0x1,
bcdUSB: 0x200,
bDeviceClass: 0xef,
bDeviceSubClass: 0x2,
bDeviceProtocol: 0x1,
bMaxPacketSize: 0x40,
idVendor: 0x1366,
idProduct: 0x1015,
bcdDevice: 0x100,
iManufacturer: 0x1,
iProduct: 0x2,
iSerialNumber: 0x3,
bNumConfigurations: 0x1,
}
[2021-07-05T12:06:30Z DEBUG jaylink] scanning 4 interfaces
[2021-07-05T12:06:30Z DEBUG jaylink] J-Link interface is #2
[2021-07-05T12:06:30Z DEBUG jaylink] legacy caps: GetHwVersion | ReadConfig | WriteConfig | SpeedInfo | GetMaxBlockSize | GetHwInfo | ResetStopTimed | SelectIf | GetCounters | GetCpuCaps | ExecCpuCmd | Swo | Register | Indicators | TestNetSpeed | GetCapsEx
[2021-07-05T12:06:30Z DEBUG jaylink::capabilities] unknown ext. capability bits: 0xA140817D8DB8EA5A33 truncated to 0x1B8EA5A33 (Reserved0 | GetHwVersion | ReadConfig | WriteConfig | SpeedInfo | GetMaxBlockSize | GetHwInfo | ResetStopTimed | SelectIf | GetCounters | GetCpuCaps | ExecCpuCmd | Swo | Register | Indicators | TestNetSpeed | GetCapsEx | HwJtagWrite)
[2021-07-05T12:06:30Z DEBUG jaylink] extended caps: GetHwVersion | ReadConfig | WriteConfig | SpeedInfo | GetMaxBlockSize | GetHwInfo | ResetStopTimed | SelectIf | GetCounters | GetCpuCaps | ExecCpuCmd | Swo | Register | Indicators | TestNetSpeed | GetCapsEx | HwJtagWrite
[2021-07-05T12:06:30Z DEBUG probe_rs::probe] Asserting reset
[2021-07-05T12:06:30Z DEBUG probe_rs::probe::jlink] Attaching to J-Link
[2021-07-05T12:06:30Z DEBUG probe_rs::probe::jlink] Attaching with protocol 'SWD'
[2021-07-05T12:06:30Z INFO probe_rs::probe::jlink] J-Link: S/N: 683287186
[2021-07-05T12:06:30Z DEBUG probe_rs::probe::jlink] J-Link: Capabilities: GetHwVersion | ReadConfig | WriteConfig | SpeedInfo | GetMaxBlockSize | GetHwInfo | ResetStopTimed | SelectIf | GetCounters | GetCpuCaps | ExecCpuCmd | Swo | Register | Indicators | TestNetSpeed | GetCapsEx | HwJtagWrite
[2021-07-05T12:06:30Z INFO probe_rs::probe::jlink] J-Link: Firmware version: J-Link OB-SAM3U128-V2-NordicSemi compiled Mar 17 2020 14:43:00
[2021-07-05T12:06:30Z INFO probe_rs::probe::jlink] J-Link: Hardware version: J-Link 1.0.0
[2021-07-05T12:06:30Z INFO probe_rs::probe::jlink] J-Link: Target voltage: 3.30 V
[2021-07-05T12:06:30Z DEBUG probe_rs::probe::jlink::swd] Performing line reset!
[2021-07-05T12:06:30Z DEBUG probe_rs::probe::jlink] Sucessfully switched to SWD
[2021-07-05T12:06:30Z DEBUG probe_rs::probe::jlink] Attached succesfully
[2021-07-05T12:06:30Z DEBUG probe_rs::config::registry] Searching registry for chip with name nRF52840_xxAA
[2021-07-05T12:06:30Z DEBUG probe_rs::probe::jlink::swd] Performing 1 transfers (0 additional transfers)
[2021-07-05T12:06:30Z DEBUG probe_rs::probe::jlink::swd] Transfer result 0: Ok(2ba01477)
[2021-07-05T12:06:30Z DEBUG probe_rs::architecture::arm::communication_interface] Debug Port version: DPv1
[2021-07-05T12:06:30Z DEBUG probe_rs::architecture::arm::dp] Reading DP register DPIDR
[2021-07-05T12:06:30Z DEBUG probe_rs::probe::jlink::swd] Performing 1 transfers (0 additional transfers)
[2021-07-05T12:06:30Z DEBUG probe_rs::probe::jlink::swd] Transfer result 0: Ok(2ba01477)
[2021-07-05T12:06:30Z DEBUG probe_rs::architecture::arm::dp] Read DP register DPIDR, value=0x2ba01477
[2021-07-05T12:06:30Z DEBUG probe_rs::architecture::arm::communication_interface] DebugPort ID: DebugPortId {
revision: 0x2,
part_no: 0xba,
version: DPv1,
min_dp_support: NotImplemented,
designer: JEP106Code({ cc: 0x04, id: 0x3b } => Some("ARM Ltd")),
}
[2021-07-05T12:06:30Z DEBUG probe_rs::architecture::arm::dp] Writing DP register ABORT, value=0x0000001e
[2021-07-05T12:06:30Z DEBUG probe_rs::probe::jlink::swd] Performing 1 transfers (0 additional transfers)
[2021-07-05T12:06:30Z DEBUG probe_rs::probe::jlink::swd] Transfer result 0: Ok(0)
[2021-07-05T12:06:30Z DEBUG probe_rs::architecture::arm::dp] Writing DP register SELECT, value=0x00000000
[2021-07-05T12:06:30Z DEBUG probe_rs::probe::jlink::swd] Performing 2 transfers (1 additional transfers)
[2021-07-05T12:06:30Z DEBUG probe_rs::probe::jlink::swd] Transfer result 0: Ok(0)
[2021-07-05T12:06:30Z DEBUG probe_rs::probe::jlink::swd] Transfer result 1: Ok(0)
[2021-07-05T12:06:30Z DEBUG probe_rs::architecture::arm::communication_interface] Requesting debug power
[2021-07-05T12:06:30Z DEBUG probe_rs::architecture::arm::dp] Writing DP register CTRL/STAT, value=0x50000001
[2021-07-05T12:06:30Z DEBUG probe_rs::probe::jlink::swd] Performing 2 transfers (1 additional transfers)
[2021-07-05T12:06:30Z DEBUG probe_rs::probe::jlink::swd] Transfer result 0: Ok(0)
[2021-07-05T12:06:30Z DEBUG probe_rs::probe::jlink::swd] Transfer result 1: Ok(0)
[2021-07-05T12:06:30Z DEBUG probe_rs::architecture::arm::dp] Reading DP register CTRL/STAT
[2021-07-05T12:06:30Z DEBUG probe_rs::probe::jlink::swd] Performing 1 transfers (0 additional transfers)
[2021-07-05T12:06:30Z DEBUG probe_rs::probe::jlink::swd] Transfer result 0: Ok(d0000041)
[2021-07-05T12:06:30Z DEBUG probe_rs::architecture::arm::dp] Read DP register CTRL/STAT, value=0xd0000041
[2021-07-05T12:06:30Z ERROR probe_rs::architecture::arm::communication_interface] Debug power request failed
....Closing session from :127.0.0.1:45102
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