PI Filter for DPLL

pi_filter.sv

module pi_filter #
( parameter DW = 10
, parameter KP = 4
, parameter KI = 6
)
( input  logic                 clk
, input  logic                 rst

, input  logic                 i_valid
, output logic                 o_valid

, input  logic signed [DW-1:0] i
, output logic signed [DW-1:0] o
);

    logic signed [DW-1:0] acc;

    always_ff @(posedge clk) begin
        if (rst) begin
            acc <= 0;
            o   <= 0;
        end else if (i_valid) begin
            acc <= acc + i;
            o   <= (acc >>> KI) + (i >>> KP);
        end
    end

    always_ff @(posedge clk) begin
        o_valid <= i_valid;
    end

endmodule