Created
February 15, 2026 13:53
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CP sign-only auto-correlation Timing metric for OFDM receiver
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| module timing_metric # | |
| ( parameter int I = 12 | |
| , parameter int N = 1024 | |
| , parameter int L = 64 | |
| , parameter int SW = $clog2(L) + 2 | |
| ) | |
| ( input logic clk | |
| , input logic signed [ I-1:0] i_re | |
| , input logic signed [ I-1:0] i_im | |
| , output logic signed [SW-1:0] o_re | |
| , output logic signed [SW-1:0] o_im | |
| ); | |
| // 1: Delay | |
| logic [N*2-1:0] line; | |
| wire q_re = i_re[I-1]; | |
| wire q_im = i_im[I-1]; | |
| wire d_re = line[1]; | |
| wire d_im = line[0]; | |
| always_ff @(posedge clk) begin | |
| line <= {{q_re, q_im}, line[N*2-1:2]}; | |
| end | |
| // 2: Products | |
| logic signed [1:0] p_re, p_im; | |
| wire rr = q_re ^ d_re; | |
| wire ii = q_im ^ d_im; | |
| wire ir = q_im ^ d_re; | |
| wire ri = q_re ^ d_im; | |
| always_ff @(posedge clk) begin | |
| p_re <= {rr & ii, rr ~^ ii}; | |
| p_im <= {ir & ~ri, ir ^ ri}; | |
| end | |
| // 3: Sum | |
| logic [L*4-1:0] hist; | |
| logic signed [SW-1:0] sum_re; | |
| logic signed [SW-1:0] sum_im; | |
| assign o_re = sum_re; | |
| assign o_im = sum_im; | |
| always_ff @(posedge clk) begin | |
| hist <= {{p_re, p_im}, hist[L*4-1:4]}; | |
| sum_re <= sum_re - $signed(hist[3:2]) + p_re; | |
| sum_im <= sum_im - $signed(hist[1:0]) + p_im; | |
| end | |
| endmodule |
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