rtl8192se-init.patch

diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c
index e5775b94f04eeb286f6856691f1f6f297dd7c37e..795436ae4da0e5d279bc6023426a97d34635b6b4 100644
--- a/drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c
+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c
@@ -1019,51 +1019,62 @@ int rtl92se_hw_init(struct ieee80211_hw *hw)
 	}
 
 	/* After read predefined TXT, we must set BB/MAC/RF
 	 * register as our requirement */
 
 	rtlphy->rfreg_chnlval[0] = rtl92s_phy_query_rf_reg(hw,
 							   (enum radio_path)0,
 							   RF_CHNLBW,
 							   RFREG_OFFSET_MASK);
 	rtlphy->rfreg_chnlval[1] = rtl92s_phy_query_rf_reg(hw,
 							   (enum radio_path)1,
 							   RF_CHNLBW,
 							   RFREG_OFFSET_MASK);
 
 	/*---- Set CCK and OFDM Block "ON"----*/
 	rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
 	rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
 
 	/*3 Set Hardware(Do nothing now) */
 	_rtl92se_hw_configure(hw);
 
 	/* Read EEPROM TX power index and PHY_REG_PG.txt to capture correct */
 	/* TX power index for different rate set. */
 	/* Get original hw reg values */
 	rtl92s_phy_get_hw_reg_originalvalue(hw);
-	/* Write correct tx power index */
+	/*
+	 * Write correct tx power index. mac80211 may not have asked us to
+	 * switch to a channel yet (e.g. right after resume), so fall back to
+	 * the current chandef or channel 1 instead of passing zero.
+	 */
+	if (hw->conf.chandef.chan)
+	        rtlphy->current_channel = hw->conf.chandef.chan->hw_value;
+
+	if (!rtlphy->current_channel ||
+	    rtlphy->current_channel > CHANNEL_MAX_NUMBER_2G)
+	        rtlphy->current_channel = 1;
+
 	rtl92s_phy_set_txpower(hw, rtlphy->current_channel);
 
 	/* We must set MAC address after firmware download. */
 	for (i = 0; i < 6; i++)
 		rtl_write_byte(rtlpriv, MACIDR0 + i, rtlefuse->dev_addr[i]);
 
 	/* EEPROM R/W workaround */
 	tmp_u1b = rtl_read_byte(rtlpriv, MAC_PINMUX_CFG);
 	rtl_write_byte(rtlpriv, MAC_PINMUX_CFG, tmp_u1b & (~BIT(3)));
 
 	rtl_write_byte(rtlpriv, 0x4d, 0x0);
 
 	if (hal_get_firmwareversion(rtlpriv) >= 0x49) {
 		tmp_byte = rtl_read_byte(rtlpriv, FW_RSVD_PG_CRTL) & (~BIT(4));
 		tmp_byte = tmp_byte | BIT(5);
 		rtl_write_byte(rtlpriv, FW_RSVD_PG_CRTL, tmp_byte);
 		rtl_write_dword(rtlpriv, TXDESC_MSK, 0xFFFFCFFF);
 	}
 
 	/* We enable high power and RA related mechanism after NIC
 	 * initialized. */
 	if (hal_get_firmwareversion(rtlpriv) >= 0x35) {
 		/* Fw v.53 and later. */
 		rtl92s_phy_set_fw_cmd(hw, FW_CMD_RA_INIT);
 	} else if (hal_get_firmwareversion(rtlpriv) == 0x34) {
diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192se/phy.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192se/phy.c
index d9ef7e1da1db452fde43d34adf2839642fe25b93..0e9b50235cc32be51743fe41c0d5535eccc28c98 100644
--- a/drivers/net/wireless/realtek/rtlwifi/rtl8192se/phy.c
+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192se/phy.c
@@ -1,41 +1,43 @@
 // SPDX-License-Identifier: GPL-2.0
 /* Copyright(c) 2009-2012  Realtek Corporation.*/
 
 #include "../wifi.h"
 #include "../pci.h"
 #include "../ps.h"
 #include "../core.h"
 #include "reg.h"
 #include "def.h"
 #include "phy.h"
 #include "rf.h"
 #include "dm.h"
 #include "fw.h"
 #include "hw.h"
 #include "table.h"
 
+static bool rtl92s_phy_channel_valid(u8 channel);
+
 u32 rtl92s_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask)
 {
 	struct rtl_priv *rtlpriv = rtl_priv(hw);
 	u32 returnvalue = 0, originalvalue, bitshift;
 
 	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "regaddr(%#x), bitmask(%#x)\n",
 		regaddr, bitmask);
 
 	originalvalue = rtl_read_dword(rtlpriv, regaddr);
 	bitshift = calculate_bit_shift(bitmask);
 	returnvalue = (originalvalue & bitmask) >> bitshift;
 
 	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "BBR MASK=0x%x Addr[0x%x]=0x%x\n",
 		bitmask, regaddr, originalvalue);
 
 	return returnvalue;
 
 }
 
 void rtl92s_phy_set_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask,
 			   u32 data)
 {
 	struct rtl_priv *rtlpriv = rtl_priv(hw);
 	u32 originalvalue, bitshift;
 
@@ -313,52 +315,56 @@ static bool _rtl92s_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
 	struct rtl_priv *rtlpriv = rtl_priv(hw);
 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
 	struct swchnlcmd precommoncmd[MAX_PRECMD_CNT];
 	u32 precommoncmdcnt;
 	struct swchnlcmd postcommoncmd[MAX_POSTCMD_CNT];
 	u32 postcommoncmdcnt;
 	struct swchnlcmd rfdependcmd[MAX_RFDEPENDCMD_CNT];
 	u32 rfdependcmdcnt;
 	struct swchnlcmd *currentcmd = NULL;
 	u8 rfpath;
 	u8 num_total_rfpath = rtlphy->num_total_rfpath;
 
 	precommoncmdcnt = 0;
 	_rtl92s_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
 			MAX_PRECMD_CNT, CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0);
 	_rtl92s_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
 			MAX_PRECMD_CNT, CMDID_END, 0, 0, 0);
 
 	postcommoncmdcnt = 0;
 
 	_rtl92s_phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++,
 			MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0);
 
 	rfdependcmdcnt = 0;
 
-	WARN_ONCE((channel < 1 || channel > 14),
-		  "rtl8192se: invalid channel for Zebra: %d\n", channel);
+        if (!rtl92s_phy_channel_valid(channel)) {
+                rtl_dbg(rtlpriv, COMP_SCAN, DBG_WARNING,
+                        "Invalid channel %u for Zebra: aborting switch\n",
+                        channel);
+                return true;
+        }
 
 	_rtl92s_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
 					 MAX_RFDEPENDCMD_CNT, CMDID_RF_WRITEREG,
 					 RF_CHNLBW, channel, 10);
 
 	_rtl92s_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
 			MAX_RFDEPENDCMD_CNT, CMDID_END, 0, 0, 0);
 
 	do {
 		switch (*stage) {
 		case 0:
 			currentcmd = &precommoncmd[*step];
 			break;
 		case 1:
 			currentcmd = &rfdependcmd[*step];
 			break;
 		case 2:
 			currentcmd = &postcommoncmd[*step];
 			break;
 		default:
 			return true;
 		}
 
 		if (currentcmd->cmdid == CMDID_END) {
 			if ((*stage) == 2) {
@@ -1096,69 +1102,81 @@ static void _rtl92s_phy_get_txpower_index(struct ieee80211_hw *hw, u8 channel,
 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
 	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 	u8 index = (channel - 1);
 
 	/* 1. CCK */
 	/* RF-A */
 	cckpowerlevel[0] = rtlefuse->txpwrlevel_cck[0][index];
 	/* RF-B */
 	cckpowerlevel[1] = rtlefuse->txpwrlevel_cck[1][index];
 
 	/* 2. OFDM for 1T or 2T */
 	if (rtlphy->rf_type == RF_1T2R || rtlphy->rf_type == RF_1T1R) {
 		/* Read HT 40 OFDM TX power */
 		ofdmpowerlevel[0] = rtlefuse->txpwrlevel_ht40_1s[0][index];
 		ofdmpowerlevel[1] = rtlefuse->txpwrlevel_ht40_1s[1][index];
 	} else if (rtlphy->rf_type == RF_2T2R) {
 		/* Read HT 40 OFDM TX power */
 		ofdmpowerlevel[0] = rtlefuse->txpwrlevel_ht40_2s[0][index];
 		ofdmpowerlevel[1] = rtlefuse->txpwrlevel_ht40_2s[1][index];
 	} else {
 		ofdmpowerlevel[0] = 0;
 		ofdmpowerlevel[1] = 0;
 	}
 }
 
+static bool rtl92s_phy_channel_valid(u8 channel)
+{
+	return channel >= 1 && channel <= CHANNEL_MAX_NUMBER_2G;
+}
+
 static void _rtl92s_phy_ccxpower_indexcheck(struct ieee80211_hw *hw,
-		u8 channel, u8 *cckpowerlevel, u8 *ofdmpowerlevel)
+	u8 channel, u8 *cckpowerlevel, u8 *ofdmpowerlevel)
 {
 	struct rtl_priv *rtlpriv = rtl_priv(hw);
 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
 
 	rtlphy->cur_cck_txpwridx = cckpowerlevel[0];
 	rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0];
 }
 
 void rtl92s_phy_set_txpower(struct ieee80211_hw *hw, u8	channel)
 {
 	struct rtl_priv *rtlpriv = rtl_priv(hw);
 	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 	/* [0]:RF-A, [1]:RF-B */
 	u8 cckpowerlevel[2], ofdmpowerlevel[2];
 
 	if (!rtlefuse->txpwr_fromeprom)
-		return;
+	        return;
+
+	if (!rtl92s_phy_channel_valid(channel)) {
+	        rtl_dbg(rtlpriv, COMP_POWER, DBG_WARNING,
+	                "Invalid channel %u for TX power setup\n",
+	                channel);
+	        return;
+	}
 
 	/* Mainly we use RF-A Tx Power to write the Tx Power registers,
 	 * but the RF-B Tx Power must be calculated by the antenna diff.
 	 * So we have to rewrite Antenna gain offset register here.
 	 * Please refer to BB register 0x80c
 	 * 1. For CCK.
 	 * 2. For OFDM 1T or 2T */
 	_rtl92s_phy_get_txpower_index(hw, channel, &cckpowerlevel[0],
 			&ofdmpowerlevel[0]);
 
 	rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
 		"Channel-%d, cckPowerLevel (A / B) = 0x%x / 0x%x, ofdmPowerLevel (A / B) = 0x%x / 0x%x\n",
 		channel, cckpowerlevel[0], cckpowerlevel[1],
 		ofdmpowerlevel[0], ofdmpowerlevel[1]);
 
 	_rtl92s_phy_ccxpower_indexcheck(hw, channel, &cckpowerlevel[0],
 			&ofdmpowerlevel[0]);
 
 	rtl92s_phy_rf6052_set_ccktxpower(hw, cckpowerlevel[0]);
 	rtl92s_phy_rf6052_set_ofdmtxpower(hw, &ofdmpowerlevel[0], channel);
 
 }
 
 void rtl92s_phy_chk_fwcmd_iodone(struct ieee80211_hw *hw)
 {
diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192se/rf.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192se/rf.c
index 17d29249a7115275e6ca7069acdff37ea31beccf..898b1096da38ff9c4d0aa7b1fb7edb4ea1082825 100644
--- a/drivers/net/wireless/realtek/rtlwifi/rtl8192se/rf.c
+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192se/rf.c
@@ -1,46 +1,57 @@
 // SPDX-License-Identifier: GPL-2.0
 /* Copyright(c) 2009-2012  Realtek Corporation.*/
 
+#include <linux/string.h>
+
 #include "../wifi.h"
 #include "reg.h"
 #include "def.h"
 #include "phy.h"
 #include "rf.h"
 #include "dm.h"
 
 
 static void _rtl92s_get_powerbase(struct ieee80211_hw *hw, u8 *p_pwrlevel,
-				  u8 chnl, u32 *ofdmbase, u32 *mcsbase,
-				  u8 *p_final_pwridx)
+                                  u8 chnl, u32 *ofdmbase, u32 *mcsbase,
+                                  u8 *p_final_pwridx)
 {
-	struct rtl_priv *rtlpriv = rtl_priv(hw);
-	struct rtl_phy *rtlphy = &(rtlpriv->phy);
-	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
-	u32 pwrbase0, pwrbase1;
-	u8 legacy_pwrdiff = 0, ht20_pwrdiff = 0;
-	u8 i, pwrlevel[4];
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_phy *rtlphy = &(rtlpriv->phy);
+        struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
+        u32 pwrbase0, pwrbase1;
+        u8 legacy_pwrdiff = 0, ht20_pwrdiff = 0;
+        u8 i, pwrlevel[4];
+
+        if (chnl < 1 || chnl > CHANNEL_MAX_NUMBER_2G) {
+                rtl_dbg(rtlpriv, COMP_POWER, DBG_WARNING,
+                        "Invalid channel %u for power base\n", chnl);
+                *ofdmbase = 0;
+                *mcsbase = 0;
+                memset(p_final_pwridx, 0, sizeof(u8) * 4);
+                return;
+        }
 
 	for (i = 0; i < 2; i++)
 		pwrlevel[i] = p_pwrlevel[i];
 
 	/* We only care about the path A for legacy. */
 	if (rtlefuse->eeprom_version < 2) {
 		pwrbase0 = pwrlevel[0] + (rtlefuse->legacy_ht_txpowerdiff & 0xf);
 	} else {
 		legacy_pwrdiff = rtlefuse->txpwr_legacyhtdiff
 						[RF90_PATH_A][chnl - 1];
 
 		/* For legacy OFDM, tx pwr always > HT OFDM pwr.
 		 * We do not care Path B
 		 * legacy OFDM pwr diff. NO BB register
 		 * to notify HW. */
 		pwrbase0 = pwrlevel[0] + legacy_pwrdiff;
 	}
 
 	pwrbase0 = (pwrbase0 << 24) | (pwrbase0 << 16) | (pwrbase0 << 8) |
 		    pwrbase0;
 	*ofdmbase = pwrbase0;
 
 	/* MCS rates */
 	if (rtlefuse->eeprom_version >= 2) {
 		/* Check HT20 to HT40 diff	*/
@@ -126,60 +137,67 @@ static void _rtl92s_set_antennadiff(struct ieee80211_hw *hw,
 
 		rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
 			"Antenna Diff from RF-B to RF-A = %d (0x%x)\n",
 			ant_pwr_diff, ant_pwr_diff & 0xf);
 
 		ant_pwr_diff &= 0xf;
 	}
 
 	/* Antenna TX power difference */
 	rtlefuse->antenna_txpwdiff[2] = 0;/* RF-D, don't care */
 	rtlefuse->antenna_txpwdiff[1] = 0;/* RF-C, don't care */
 	rtlefuse->antenna_txpwdiff[0] = (u8)(ant_pwr_diff);	/* RF-B */
 
 	u4reg_val = rtlefuse->antenna_txpwdiff[2] << 8 |
 				rtlefuse->antenna_txpwdiff[1] << 4 |
 				rtlefuse->antenna_txpwdiff[0];
 
 	rtl_set_bbreg(hw, RFPGA0_TXGAINSTAGE, (BXBTXAGC | BXCTXAGC | BXDTXAGC),
 		      u4reg_val);
 
 	rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD, "Write BCD-Diff(0x%x) = 0x%x\n",
 		RFPGA0_TXGAINSTAGE, u4reg_val);
 }
 
 static void _rtl92s_get_txpower_writeval_byregulatory(struct ieee80211_hw *hw,
-						      u8 chnl, u8 index,
-						      u32 pwrbase0,
-						      u32 pwrbase1,
-						      u32 *p_outwrite_val)
+                                                      u8 chnl, u8 index,
+                                                      u32 pwrbase0,
+                                                      u32 pwrbase1,
+                                                      u32 *p_outwrite_val)
 {
-	struct rtl_priv *rtlpriv = rtl_priv(hw);
-	struct rtl_phy *rtlphy = &(rtlpriv->phy);
-	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
-	u8 i, chnlgroup, pwrdiff_limit[4];
-	u32 writeval, customer_limit;
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_phy *rtlphy = &(rtlpriv->phy);
+        struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
+        u8 i, chnlgroup, pwrdiff_limit[4];
+        u32 writeval, customer_limit;
+
+        if (chnl < 1 || chnl > CHANNEL_MAX_NUMBER_2G) {
+                rtl_dbg(rtlpriv, COMP_POWER, DBG_WARNING,
+                        "Invalid channel %u for writeval\n", chnl);
+                *p_outwrite_val = (index < 2) ? pwrbase0 : pwrbase1;
+                return;
+        }
 
 	/* Index 0 & 1= legacy OFDM, 2-5=HT_MCS rate */
 	switch (rtlefuse->eeprom_regulatory) {
 	case 0:
 		/* Realtek better performance increase power diff
 		 * defined by Realtek for large power */
 		chnlgroup = 0;
 
 		writeval = rtlphy->mcs_offset[chnlgroup][index] +
 				((index < 2) ? pwrbase0 : pwrbase1);
 
 		rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
 			"RTK better performance, writeval = 0x%x\n", writeval);
 		break;
 	case 1:
 		/* Realtek regulatory increase power diff defined
 		 * by Realtek for regulatory */
 		if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) {
 			writeval = ((index < 2) ? pwrbase0 : pwrbase1);
 
 			rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
 				"Realtek regulatory, 40MHz, writeval = 0x%x\n",
 				writeval);
 		} else {
 			chnlgroup = 0;
@@ -319,58 +337,66 @@ static void _rtl92s_write_ofdm_powerreg(struct ieee80211_hw *hw,
 		 * Protect Path B pwr over or under flow. We need to calculate
 		 * upper and lower bound of path A tx power. */
 		if (rtlphy->rf_type == RF_2T2R) {
 			/* Diff=-8~-1 */
 			if (rf_pwr_diff >= 8) {
 				/* Prevent underflow!! */
 				if (rfa_pwr[i] < rfa_lower_bound)
 					rfa_pwr[i] = rfa_lower_bound;
 			/* Diff = 0-7 */
 			} else if (rf_pwr_diff >= 1) {
 				/* Prevent overflow */
 				if (rfa_pwr[i] > rfa_upper_bound)
 					rfa_pwr[i] = rfa_upper_bound;
 			}
 		}
 
 	}
 
 	writeval = (rfa_pwr[3] << 24) | (rfa_pwr[2] << 16) | (rfa_pwr[1] << 8) |
 				rfa_pwr[0];
 
 	rtl_set_bbreg(hw, regoffset[index], 0x7f7f7f7f, writeval);
 }
 
 void rtl92s_phy_rf6052_set_ofdmtxpower(struct ieee80211_hw *hw,
-				       u8 *p_pwrlevel, u8 chnl)
+	                               u8 *p_pwrlevel, u8 chnl)
 {
+	struct rtl_priv *rtlpriv = rtl_priv(hw);
 	u32 writeval, pwrbase0, pwrbase1;
 	u8 index = 0;
 	u8 finalpwr_idx[4];
 
+	if (chnl < 1 || chnl > CHANNEL_MAX_NUMBER_2G) {
+	        rtl_dbg(rtlpriv, COMP_POWER, DBG_WARNING,
+	                "Invalid channel %u for OFDM TX power\n",
+	                chnl);
+	        return;
+	}
+
 	_rtl92s_get_powerbase(hw, p_pwrlevel, chnl, &pwrbase0, &pwrbase1,
-			&finalpwr_idx[0]);
+	                &finalpwr_idx[0]);
 	_rtl92s_set_antennadiff(hw, &finalpwr_idx[0]);
 
 	for (index = 0; index < 6; index++) {
 		_rtl92s_get_txpower_writeval_byregulatory(hw, chnl, index,
 				pwrbase0, pwrbase1, &writeval);
 
 		_rtl92s_write_ofdm_powerreg(hw, index, writeval);
 	}
 }
 
 void rtl92s_phy_rf6052_set_ccktxpower(struct ieee80211_hw *hw, u8 pwrlevel)
 {
 	struct rtl_priv *rtlpriv = rtl_priv(hw);
 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 	u32 txagc = 0;
 	bool dont_inc_cck_or_turboscanoff = false;
 
 	if (((rtlefuse->eeprom_version >= 2) &&
 	      (rtlefuse->txpwr_safetyflag == 1)) ||
 	      ((rtlefuse->eeprom_version >= 2) &&
 	      (rtlefuse->eeprom_regulatory != 0)))
 		dont_inc_cck_or_turboscanoff = true;
 
 	if (mac->act_scanning) {
diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192se/sw.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192se/sw.c
index 1cf801feb45e2cdbbe1bf69db45ec3595644bcf0..5279ea14c76d19cfa523adee4f75d40c1cff986a 100644
--- a/drivers/net/wireless/realtek/rtlwifi/rtl8192se/sw.c
+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192se/sw.c
@@ -69,50 +69,59 @@ static void rtl92se_fw_cb(const struct firmware *firmware, void *context)
 		rtlpriv->max_fw_size = 0;
 		goto exit;
 	}
 	if (firmware->size > rtlpriv->max_fw_size) {
 		pr_err("Firmware is too big!\n");
 		rtlpriv->max_fw_size = 0;
 		release_firmware(firmware);
 		goto exit;
 	}
 	pfirmware = (struct rt_firmware *)rtlpriv->rtlhal.pfirmware;
 	memcpy(pfirmware->sz_fw_tmpbuffer, firmware->data, firmware->size);
 	pfirmware->sz_fw_tmpbufferlen = firmware->size;
 	release_firmware(firmware);
 exit:
 	complete(&rtlpriv->firmware_loading_complete);
 }
 
 static int rtl92s_init_sw_vars(struct ieee80211_hw *hw)
 {
 	struct rtl_priv *rtlpriv = rtl_priv(hw);
 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 	int err = 0;
 	u16 earlyrxthreshold = 7;
 	char *fw_name = "rtlwifi/rtl8192sefw.bin";
 
+	/* Ensure we never run the TX power setup with an invalid channel. */
+	if (hw->conf.chandef.chan)
+	        rtlpriv->phy.current_channel =
+	                hw->conf.chandef.chan->hw_value;
+
+	if (!rtlpriv->phy.current_channel ||
+	    rtlpriv->phy.current_channel > CHANNEL_MAX_NUMBER_2G)
+	        rtlpriv->phy.current_channel = 1;
+
 	rtlpriv->dm.dm_initialgain_enable = true;
 	rtlpriv->dm.dm_flag = 0;
 	rtlpriv->dm.disable_framebursting = false;
 	rtlpriv->dm.thermalvalue = 0;
 	rtlpriv->dm.useramask = true;
 
 	/* compatible 5G band 91se just 2.4G band & smsp */
 	rtlpriv->rtlhal.current_bandtype = BAND_ON_2_4G;
 	rtlpriv->rtlhal.bandset = BAND_ON_2_4G;
 	rtlpriv->rtlhal.macphymode = SINGLEMAC_SINGLEPHY;
 
 	rtlpci->transmit_config = 0;
 
 	rtlpci->receive_config =
 			RCR_APPFCS |
 			RCR_APWRMGT |
 			/*RCR_ADD3 |*/
 			RCR_AMF	|
 			RCR_ADF |
 			RCR_APP_MIC |
 			RCR_APP_ICV |
 			RCR_AICV |
 			/* Accept ICV error, CRC32 Error */
 			RCR_ACRC32 |
 			RCR_AB |